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  • The bulk MOSFETs have a capacitance equivalent thickness (CET) of 1.8 nm and have been fabricated with identical back-end processes. The gate-to-channel capacitance is 19 fF/.

Универсальный англо-русский словарь. Академик.ру. 2011.

Смотреть что такое 'bulk CMOS' в других словарях:

  • bulk CMOS process — jungtinių MOP darinių su puslaidininkiniu padėklu technologija statusas T sritis radioelektronika atitikmenys: angl. bulk CMOS process; bulk complementary MOS process vok. volumenkomplementäre MOS Technologie, f rus. КМОП технология на… … Radioelektronikos terminų žodynas

  • bulk complementary MOS process — jungtinių MOP darinių su puslaidininkiniu padėklu technologija statusas T sritis radioelektronika atitikmenys: angl. bulk CMOS process; bulk complementary MOS process vok. volumenkomplementäre MOS Technologie, f rus. КМОП технология на… … Radioelektronikos terminų žodynas

  • Bulk acoustic wave — BAW Filter (engl. bulk acoustic wave) sind elektronische Filter mit Bandpass Charakteristik. Sie kommen in der Hochfrequenztechnik beispielsweise bei Mobilfunk und WLAN zum Einsatz. Die Funktionsweise ist mit der eines Oberflächenwellenfilters… … Deutsch Wikipedia

  • technologie CMOS sur substrat semi-conducteur — jungtinių MOP darinių su puslaidininkiniu padėklu technologija statusas T sritis radioelektronika atitikmenys: angl. bulk CMOS process; bulk complementary MOS process vok. volumenkomplementäre MOS Technologie, f rus. КМОП технология на… … Radioelektronikos terminų žodynas

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  • Silicon on insulator — technology (SOI) refers to the use of a layered silicon insulator silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby… … Wikipedia

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  • Titan (microprocessor) — Titan is a family of 32 bit Power Architecture based microprocessors designed by Applied Micro Circuits Corporation (AMCC).It is designed to be the foundation of embedded processors and system on a chip (SoC) solutions. While being high… … Wikipedia

  • jungtinių MOP darinių su puslaidininkiniu padėklu technologija — statusas T sritis radioelektronika atitikmenys: angl. bulk CMOS process; bulk complementary MOS process vok. volumenkomplementäre MOS Technologie, f rus. КМОП технология на полупроводниковой подложке, f pranc. technologie CMOS sur substrat semi… … Radioelektronikos terminų žodynas

  • volumenkomplementäre MOS-Technologie — jungtinių MOP darinių su puslaidininkiniu padėklu technologija statusas T sritis radioelektronika atitikmenys: angl. bulk CMOS process; bulk complementary MOS process vok. volumenkomplementäre MOS Technologie, f rus. КМОП технология на… … Radioelektronikos terminų žodynas

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  • Nanoscale CMOS. Innovative Materials, Modeling and Characterization, Francis Balestra. This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS… ПодробнееКупить за 21150.85 рубэлектронная книга

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4 IEEE TRANSACTIONS ON ELECTRON DEVICES

IEEE

Fig. 6.

Proof

Comparison of (a) transverse stress profiles and (b) STI stress-induced hole mobility variations for planar versus trigate (WSTRIPE = 20 nm) bulk

MOSFETs using Taurus 3-D [11]. The silicon stripe height is 10 nm for the trigate bulk MOSFETs, which provides for more uniform channel mobility because

of reduced STI-induced channel stress.

Fig. 7.

CESL-induced stress distribution in planar and trigate bulk MOSFETs. The CESL is assumed to be a 30-nm-thick silicon nitride with 2-GPa tensile

stress. LG = 20 nm, tox = 9 Å, gate electrode thickness (TGATE) = 40 nm, spacer width (LSPACER) = 20 nm, WSTRIPE = 20 nm, WSPACING = 20, and HSTRIPE = 10 nm.

132IV. IMPACT OF RANDOM VARIATIONS

133Here, LERand RDF-induced variations are compared for

134the three MOSFET structures. Gate LER profiles are sampled

135from a scanning electron micrograph of extreme ultraviolet

136resist lines. On average, these lines have an LER (3σ) value

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of 4 nm and a line width roughness (LWR) value of 6.4 nm. 137 The distance between the consecutive sampling points of the 138 LER profiles is approximately 0.8 nm. Examples of simulated 139 structures with different gate LER profiles are shown in Fig. 8. 140 The source and drain junction profiles are assumed to have 141

SUN et al.: STUDY OF PLANAR MOSFET, SOI FinFET, AND TRIGATE MOSFET DESIGNS

5

Fig. 10. LERand RDFinduced variations in trigate bulk MOSFET, SOI

Fig. 8. Examples of simulated gate electrodes with different LER profiles.

FinFET, and planar bulk MOSFET.

LG = 20 nm, and tSi = 0.6 LG =

12 nm.

IEEE

Fig. 9. LER-induced variation in trigate bulk MOSFET, SOI FinFET, and

planar bulk MOSFET. LG = 20 nm, and tSi = 0.6 LG = 12 nm.

142 the same LER as the gate electrode to simulate the worst case

143 scenario; thus, Le will have the same roughness profile as

144

LG. The RDF profiles are generated using kinetic Monte Carlo

145 simulations [9] on the MOSFET structures with gate LER.

146

Three-dimensional device simulations are performed for the

147 optimized nominal designs to investigate the effects of LER

148 only and also to investigate the effects of LER, together with

149

RDF, in the source/drain and channel regions.

150

Fig. 9 shows the gate LER-induced VT variations (σVT )

151 for the SOI FinFET, planar bulk MOSFET, and trigate bulk

152

MOSFET with tSi = 0.6 LG. The variation is smallest for the

153 trigate bulk MOSFET design due to its superior electrostatic

154 integrity. The SOI FinFET has VT variation comparable to that

155 of the planar bulk MOSFET. This is because the two sidewall

156 gates of the FinFET have discrete different gate lengths due to

Fig. 11. Effect of tSi on LERand RDFinduced variations. LG = 20 nm.

157

gate LWR, whereas the effects of gate LWR on planar bulk

158

MOSFETs are somewhat averaged across the channel width.

(a) tSi = 0.6 LG = 12 nm. (b) tSi = 0.8 LG = 16 nm.

159

VT variations due to the presence of both LER and RDF are

160 shown in Fig. 10. VT lowering (where

VT is equal to the

gradient regions increases with smaller WSTRIPE [12] and 167

161

VT value of the nominal design subtracted by the mean VT

also because of larger LER-induced variation, the SOI FinFET 168

162 value of the MOSFET structures with gate LER and RDF)

does not provide for reduced random variation, as compared 169

163 is smallest for the trigate bulk MOSFET due to its superior

with the trigate bulk MOSFET design, although there are no 170

164 electrostatic integrity. Overall, the trigate bulk MOSFET also

channel dopants in the SOI FinFET. Fig. 11 shows the effect 171

165 shows comparable random VT

variation as the SOI FinFET.

of tSi on the random variation. For the trigate bulk MOSFET, 172

Download cinterion wireless modules port devices driver. 166

Because VT variation induced

by RDF

in the source/drain

tSi = 0.6 LG yields the smallest random variation, whereas 173

6

174 for the planar bulk MOSFET, tSi = 0.8 LG is beneficial for 175 reduced RDF-induced variability since the average number of 176 channel dopants is smaller.

177

V. CONCLUSION

178The impact of process-induced systematic and random vari-

179ations on transistor performance has been investigated for three

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180different transistor structures. As compared with the planar bulk

181MOSFET and SOI FinFET, the trigate bulk MOSFET design

182shows the least variability and the best nominal performance.

Mosfet bulk current

183Thus, it is a promising device architecture for transistor scaling

184to the end of the technology roadmap.

IEEE TRANSACTIONS ON ELECTRON DEVICES

[7] X. Sun and T.-J. King Liu, “Scale length assessment of the tri-gate 206 bulk MOSFET design,” IEEE Trans. Electron Devices, vol. 56, no. 11, 207

pp. 2840–2842, Nov. 2009.

208

[8] A. Hokazono, H. Itokawa, N. Kusunoki, I. Mizushima,

S. Inaba, 209

S. Kawanaka, and Y. Toyoshima, “Steep channel & halo profiles utilizing 210 boron-diffusion-barrier layers (Si:C) for 32 nm node and beyond,” in VLSI 211

Symp. Tech. Dig., 2008, pp. 112–113.

212

[9] Synopsys, Inc., Mountain View, CA, Sentaurus User’s Manual, 2009.06, 213 2009. 214

Cable

[10]G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive 215 current reduction caused by transistor layout and trench isolation induced 216

stress,” in IEDM Tech. Dig., 1999, pp. 827–830.

217

[11] Taurus User’s Manual, Synopsys, Inc., Mountain View, CA.

218

AQ1

[12]V. Varadarajan, L. Smith, S. Balasubramanian, and T.-J. King Liu, “Multi219 gate FET design for tolerance to statistical dopant fluctuations,” in 220

Proc. IEEE Silicon Nanoelectron. Workshop, 2006, pp. 137–138.

221

185

REFERENCES

Xin Sun, photograph and biography not available at the time of publication. 222

Mosfet Bulk Current

Bulk Mosfet

186[1] H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki, “Challenge:

187Variability characterization and modeling for 65to 90-nm process,” in

188

Proc. Custom Integr. Circuits Conf., 2005, pp. 593–599.

Victor Moroz, photograph and biography not available

Capture one 20 free crack for mac. at the time of 223

189

[2]

A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva,

publication.

224

190

IEEE

“Simulation of intrinsic parameter fluctuations in decananometer and

191

nanometer-scale MOSFETs,” IEEE Trans. Electron Devices, vol. 50,

192

no. 9, pp. 1837–1852, Sep. 2003.

193

[3] R.-H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: From

Nattapol Damrongplasit, photograph and biography not available at the time 225

194

bulk to SOI to bulk,” IEEE Trans. Electron Devices, vol. 39, no. 7,

of publication.

226

195

pp. 1704–1710, Jul. 1992.

196

[4] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling

197

theory for double-gate SOI MOSFETs,” IEEE Trans. Electron Devices,

198

vol. 40, no. 12, pp. 2326–2329, Dec. 1993.

Changhwan Shin, photograph and biography not available at the time of 227

199

[5]

D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized scale length for

Proof

200

two-dimensional effects in MOSFETs,” IEEE Electron Device Lett.,

publication.

228

201

vol. 19, no. 10, pp. 385–387, Oct. 1998.

202

[6]

X. Sun, Q. Lu, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S. Ikeda,

203

C. Shin, and T.-J. King Liu, “Tri-gate bulk MOSFET design for CMOS

Tsu-Jae King Liu, photograph and biography not available at the time of 229

204

scaling to the end of the roadmap,” IEEE Electron Device Lett., vol. 29,

205

no. 5, pp. 491–493, May 2008.

publication.

230

AUTHOR QUERIES

AUTHOR PLEASE ANSWER ALL QUERIES

AQ1 = Please provide year of publication in Ref. [11].

END OF ALL QUERIES

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